/*
 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "stih41x.dtsi"
#include "stih415-clock.dtsi"
#include "stih415-pinctrl.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/stih415-resets.h>
/ {

	L2: cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0xfffe2000 0x1000>;
		arm,data-latency = <3 2 2>;
		arm,tag-latency = <1 1 1>;
		cache-unified;
		cache-level = <2>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;
		compatible	= "simple-bus";

		powerdown: powerdown-controller {
			#reset-cells = <1>;
			compatible = "st,stih415-powerdown";
		};

		softreset: softreset-controller {
			#reset-cells = <1>;
			compatible = "st,stih415-softreset";
		};

		syscfg_sbc: sbc-syscfg@fe600000{
			compatible      = "st,stih415-sbc-syscfg", "syscon";
			reg		= <0xfe600000 0xb4>;
		};

		syscfg_front: front-syscfg@fee10000{
			compatible      = "st,stih415-front-syscfg", "syscon";
			reg		= <0xfee10000 0x194>;
		};

		syscfg_rear: rear-syscfg@fe830000{
			compatible      = "st,stih415-rear-syscfg", "syscon";
			reg		= <0xfe830000 0x190>;
		};

		/* MPE syscfgs */
		syscfg_left: left-syscfg@fd690000{
			compatible      = "st,stih415-left-syscfg", "syscon";
			reg		= <0xfd690000 0x78>;
		};

		syscfg_right: right-syscfg@fd320000{
			compatible      = "st,stih415-right-syscfg", "syscon";
			reg		= <0xfd320000 0x180>;
		};

		syscfg_system: system-syscfg@fdde0000  {
			compatible      = "st,stih415-system-syscfg", "syscon";
			reg		= <0xfdde0000 0x15c>;
		};

		syscfg_lpm: lpm-syscfg@fe4b5100{
			compatible      = "st,stih415-lpm-syscfg", "syscon";
			reg		= <0xfe4b5100 0x08>;
		};

		serial2: serial@fed32000 {
			compatible	= "st,asc";
			status 		= "disabled";
			reg		= <0xfed32000 0x2c>;
			interrupts	= <0 197 0>;
			pinctrl-names 	= "default";
			pinctrl-0 	= <&pinctrl_serial2>;
			clocks		= <&clk_s_a0_ls CLK_ICN_REG>;
		};

		/* SBC comms block ASCs in SASG1 */
		sbc_serial1: serial@fe531000 {
			compatible	= "st,asc";
			status 		= "disabled";
			reg		= <0xfe531000 0x2c>;
			interrupts	= <0 210 0>;
			clocks		= <&clk_sysin>;
			pinctrl-names 	= "default";
			pinctrl-0	= <&pinctrl_sbc_serial1>;
		};

		i2c@fed40000 {
			compatible	= "st,comms-ssc4-i2c";
			reg		= <0xfed40000 0x110>;
			interrupts	= <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks		= <&clk_s_a0_ls CLK_ICN_REG>;
			clock-names	= "ssc";
			clock-frequency = <400000>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_i2c0_default>;

			status		= "disabled";
		};

		i2c@fed41000 {
			compatible	= "st,comms-ssc4-i2c";
			reg		= <0xfed41000 0x110>;
			interrupts	= <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks		= <&clk_s_a0_ls CLK_ICN_REG>;
			clock-names	= "ssc";
			clock-frequency = <400000>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_i2c1_default>;

			status		= "disabled";
		};

		i2c@fe540000 {
			compatible	= "st,comms-ssc4-i2c";
			reg		= <0xfe540000 0x110>;
			interrupts	= <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
			clocks		= <&clk_sysin>;
			clock-names	= "ssc";
			clock-frequency = <400000>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_sbc_i2c0_default>;

			status		= "disabled";
		};

		i2c@fe541000 {
			compatible	= "st,comms-ssc4-i2c";
			reg		= <0xfe541000 0x110>;
			interrupts	= <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
			clocks		= <&clk_sysin>;
			clock-names	= "ssc";
			clock-frequency = <400000>;
			pinctrl-names	= "default";
			pinctrl-0	= <&pinctrl_sbc_i2c1_default>;

			status		= "disabled";
		};

		ethernet0: dwmac@fe810000 {
			device_type 	= "network";
			compatible	= "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
			status 		= "disabled";

			reg		= <0xfe810000 0x8000>;
			reg-names	= "stmmaceth";

			interrupts 	= <0 147 0>, <0 148 0>, <0 149 0>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
			resets			= <&softreset STIH415_ETH0_SOFTRESET>;
			reset-names		= "stmmaceth";

			snps,pbl 	= <32>;
			snps,mixed-burst;
			snps,force_sf_dma_mode;

			st,syscon	= <&syscfg_rear 0x148>;

			pinctrl-names 	= "default";
			pinctrl-0	= <&pinctrl_mii0>;
			clock-names	= "stmmaceth", "sti-ethclk";
			clocks		= <&clk_s_a1_ls CLK_ICN_IF_2>, <&clk_s_a1_ls CLK_GMAC0_PHY>;
		};

		ethernet1: dwmac@fef08000 {
			device_type = "network";
			compatible	= "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
			status 		= "disabled";
			reg		= <0xfef08000 0x8000>;
			reg-names	= "stmmaceth";
			interrupts 	= <0 150 0>, <0 151 0>, <0 152 0>;
			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";

			snps,pbl	= <32>;
			snps,mixed-burst;
			snps,force_sf_dma_mode;

			st,syscon		= <&syscfg_sbc 0x74>;

			resets			= <&softreset STIH415_ETH1_SOFTRESET>;
			reset-names		= "stmmaceth";
			pinctrl-names 	= "default";
			pinctrl-0	= <&pinctrl_mii1>;
			clock-names	= "stmmaceth", "sti-ethclk";
			clocks		= <&clk_s_a0_ls CLK_ICN_REG>, <&clk_s_a0_ls CLK_ETH1_PHY>;
		};

		rc: rc@fe518000 {
			compatible	= "st,comms-irb";
			reg		= <0xfe518000 0x234>;
			interrupts	=  <0 203 0>;
			clocks		= <&clk_sysin>;
			rx-mode		= "infrared";
			pinctrl-names 	= "default";
			pinctrl-0	= <&pinctrl_ir>;
			resets		= <&softreset STIH415_IRB_SOFTRESET>;
		};

		keyscan: keyscan@fe4b0000 {
			compatible = "st,sti-keyscan";
			status = "disabled";
			reg = <0xfe4b0000 0x2000>;
			interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
			clocks = <&clk_sysin>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_keyscan>;
			resets	= <&powerdown STIH415_KEYSCAN_POWERDOWN>,
				  <&softreset STIH415_KEYSCAN_SOFTRESET>;
		};

		mmc0: sdhci@fe81e000 {
			compatible      = "st,sdhci";
			status          = "disabled";
			reg             = <0xfe81e000 0x1000>;
			interrupts      = <GIC_SPI 145 IRQ_TYPE_NONE>;
			interrupt-names = "mmcirq";
			pinctrl-names   = "default";
			pinctrl-0       = <&pinctrl_mmc0>;
			clock-names     = "mmc";
			clocks          = <&clk_s_a1_ls 1>;
		};
	};
};
